The bottleneck moves to assembly
The market has been captivated by the front of the chain: Nvidia designs the powerful GPUs, TSMC physically prints them, ASML supplies the lithography equipment, and memory makers stack HBM. The truth is that this view of the industry rests on yesterday's technology. Gone are the days when every gain in performance came from a smaller process node (physically shrinking the circuits on a silicon wafer). Today, added compute comes from cleverly packing more and more separate parts onto a single plane. That means tall vertical HBM memory stacks and large logic dies (chiplets) placed on a shared interposer. The technological bottleneck, and with it the margins and investor attention, is decisively moving off the silicon layer and into the process known as packaging.