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Investment thesis · Live

The technological bottleneck in AI is shifting from silicon structures toward advanced chip packaging

Shrinking transistors physically is getting harder, so the fight for more compute is moving into advanced packaging. The capabilities the industry now depends on are controlled by a handful of suppliers of precision metrology and assembly equipment.

Published July 7, 2026 · 180-day horizon · technology

Basket return
-6.9%
equal weight, since publication
The market over the same window
+2.3%
benchmark for this basket
Edge over the market
-9.2%
in percentage points
Causal chain: Demand for powerful AI accelerators stays high → The end of easy transistor scaling moves innovation to integration (chiplets and HBM) → The HBM4 standard raises the bar for memory stacking (expected 2026) → Advanced packaging becomes the bottleneck for the entire industry → TSMC fabs and OSATs sharply double their purchases of assembly and test equipment → Leaders in modern chip bonding technology (Besi, ASMPT) → Top makers of metrology and precision inspection equipment (Camtek, Onto)

What this thesis rests on

Each one is a statement that has to be true. When a filing says otherwise, the thesis is in trouble, and this is where we say so.

  1. TSMC confirms in its quarterly results or annual filing before 31 December 2026 that advanced packaging (CoWoS) capacity is being roughly doubled again, with 2026 capital expenditure at or above the 2025 level.

    operational · Unverified

  2. BE Semiconductor Industries discloses volume production orders or shipments of hybrid bonding systems for HBM4 or logic in a quarterly report published within the 180-day horizon.

    operational · Unverified

  3. ASMPT reports semiconductor solutions segment bookings at least 20% higher year on year in both quarterly reports after publication, offsetting its mainstream assembly weakness.

    financial · Unverified

  4. Camtek reports quarterly revenue of at least USD 115 million in each of the two quarters following publication.

    financial · Unverified

  5. Onto Innovation's reported gross margin stays above 50% in the two quarters after publication, with no disclosed price concessions to its largest advanced packaging customer.

    competitive · Unverified

The bottleneck moves to assembly

The market has been captivated by the front of the chain: Nvidia designs the powerful GPUs, TSMC physically prints them, ASML supplies the lithography equipment, and memory makers stack HBM. The truth is that this view of the industry rests on yesterday's technology. Gone are the days when every gain in performance came from a smaller process node (physically shrinking the circuits on a silicon wafer). Today, added compute comes from cleverly packing more and more separate parts onto a single plane. That means tall vertical HBM memory stacks and large logic dies (chiplets) placed on a shared interposer. The technological bottleneck, and with it the margins and investor attention, is decisively moving off the silicon layer and into the process known as packaging.

This thesis, over time

What has happened since publication. Every entry is computed as of its own date, from price history.

August 21, 2026

Day 45 of 180: basket -6.9%

The first quarter of the horizon is behind this thesis. The equal-weight basket stands at -6.9% since publication day. The benchmark (S&P 500) returned +1.8% over the same window, so the basket trails its market by 8.7 percentage points. The strongest contributor is CAMT (+4.7%), the weakest is 0522 (-16.8%). 135 days remain until the verdict.

Open the interactive thesis

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This is analysis, not investment advice and not a recommendation to buy or sell anything. We publish it and track it in public, mistakes included. Any decision is yours and yours alone.