Investment thesis · Live
The AI bottleneck is migrating from the wafer to the package, and four back-end tool makers own the choke point
As transistor scaling stalls, AI gains come from packaging, and a few back-end tool makers own the bonding and inspection choke point.
Published July 7, 2026 · 180-day horizon · technology
The causal chain: AI accelerator demand keeps scaling → Slower transistor scaling shifts gains to chiplets + HBM integration → HBM4 raises stack height and layer count (2026) → Advanced packaging becomes the binding bottleneck → TSMC/OSATs ~double back-end capacity; more bonding and inspection per unit → Bonding tool leaders (Besi, ASMPT) → Packaging metrology/inspection (Camtek, Onto)
The bottleneck is moving to the back end
The consensus AI hardware trade is built around the front end: Nvidia designs, TSMC fabricates, ASML supplies the lithography, and a few memory makers stack HBM. That framing is now a generation behind the actual constraint. Transistor scaling has slowed to the point where most of the incremental performance in an AI accelerator no longer comes from a smaller node. It comes from packaging more silicon together: stacking taller HBM, bonding more logic chiplets side by side and on top of each other, and doing it on ever larger interposers. The value, and the bottleneck, is migrating from the wafer to the package.
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